ICS (Architecture)

Fudan University / 2020 Spring

Note: This is the first assignment for this course, you should read the guidelines first. This assignment will make up 20% of the final score.

This assignment will due on Apr 6 before the course start, and you must pass all the tests before submitting your work, for detailed information about checker configuration, also refer to the guidelines.

Description

In this assignment, you are going to implement Single-Cycle MIPS CPU according to slides and textbook. Your CPU need support instructions including: add，sub，and，or，slt，addi，andi，ori，slti，sw，lw，j，nop，beq，bne, jal, jr, sra, sll, srl. For unfamiliar instructions, please refer to our textbook Digital Design and Computer Architecture's Appendix B.

You have to follow our variable naming rules and framework as shown in cpu_tb.sv, which mainly refer to our textbook, since our graders are based on them.

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module cpu_tb();
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/*
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 * grader
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 */
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​
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mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data));
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imem imem(.a(pc[7:2]), .rd(instr));
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dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data));
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endmodule

After finishing CPU, you must run simulation to check if your CPU works well. This assignment's tests are all listed in assignment/benchtest

Report Requirements

• There's no need to include simulation results (e.g. wave plots) in your report, since you have passed all the benchtests.
• You should list all the references you find useful during your implementation, especially for the pictures you include in your report (We recommend you draw pictures on your own).
• You are encouraged to offer some interesting and useful benchtests (not included in ours) in your report (no more than 5% bonus).