This assignment will make up 20% of the final score. It will due on Apr 27, and you must pass all the tests before submitting your work. Recently we've made some changes to grade your work automatically, please refer to checker guidelines for details.
Pipelining is a technique where multiple instructions are overlapped during execution. It reduces CPI so that total CPU time consumption is dramatically reduced compared to non-pipelining. All modern high-performance microprocessors are pipelined.
From now on, we'll measure CPI of your CPU, and you may alter 76th-79th lines of cpu_tb.sv
to fit into yours.
xcycle cycle 1;
if (mips.dp.flushD mips.dp.haz.stallD)
instr_count instr_count 1;
However, because multiple instructions are handled concurrently in a pipelined system, there exists possibility of hazards, which need special solution.
In this assignment, you are going to implement Pipeline MIPS CPU according to slides and textbook.
Your CPU needs to support instructions: add,sub,and,or,slt,addi,andi,ori,slti,sw,lw,j,nop,beq,bne, jal, jr, sra, sll, srl. For unfamiliar instructions, please refer to our textbook Digital Design and Computer Architecture's Appendix B.
You have to follow our I/O port naming as shown in cpu_tb.sv
, on which our graders are based. (Same as in textbook)
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module cpu_tb();
/*
* grader
*/
mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data));
imem imem(.a(pc[7:2]), .rd(instr));
dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data));
endmodule
Before submission, you must run simulation to check if your CPU works well. This assignment's tests are all listed in assignment-2/benchtest